(a) Field of the Invention
The present invention relates to a method for manufacturing an interconnection structure in a semiconductor device and, more particularly, to a method for forming a tungsten film or plug in a via-hole for an interconnection structure.
(b) Description of the Related Art
Recently, the aspect ratio of via-holes formed on an interconnection layer or on a diffused layer is increased in a ULSI device having a higher integration density. Thus, satisfactory connection between via-hole and the underlying diffused layer or lower interconnection layer is difficult to obtain by using a conventional aluminum (Al) single-layer interconnects. In view of this, chemical vapor deposited (CVD) tungsten (W) films are increasingly used to bury the via-holes having a high aspect ratio.
Examples of the methods for forming a CVD tungsten film on an interlayer dielectric film include a selective growth technique, such as described in JP-A-4(1992)-298031 and 5(1993)-90199, wherein tungsten film is selectively formed only in via-holes formed in an interlayer dielectric film and a blanket technique wherein a tungsten film is first formed on the entire surface including within via-holes and subsequent etch-back of the tungsten film to remove the tungsten film from the interlayer dielectric film.
The selective growth technique has advantages of low costs and reduced steps as compared to the blanket technique. However, the selective growth technique has a disadvantage of an unstable process in a mass production, which involves defective selective growth and degradation in electric characteristics of the resultant tungsten film, as generally involved in a process using the difference in the surface characteristics.
In the blanket technique, a barrier metal which is also used in the conventional Al interconnects can be used as an adhesive layer, which allows the tungsten layer effectively deposited on the underlying layer of any material and within different via-holes of any depth. Accordingly, the blanket technique is increasingly used as a key technology for the high aspect ratio via-holes.
FIGS. 1A and 1B show a process for the blanket technique, and FIG. 2 is a timing chart for introduction of gases during the process. In FIG. 1A, a gate electrode 14 is formed on a silicon substrate 11 with an intervention of a gate insulator film not shown, followed by ion-implantation into the substrate 11 to form diffused regions 13 for source and drain. Then, an interlayer dielectric film 15A made of boron-doped phospho-silicate glass (BPSG), followed by patterning to form a via-hole 16 on the diffused regions 13. Subsequently, a Ti--Ni barrier metal layer 19 and a silicon layer 23 are consecutively deposited on the entire surface, wherein the silicon (Si) film 23 is deposited by thermal decomposition of SiH.sub.4, as shown in FIG. 1A, during time interval between ts1 and ts2 as shown in FIG. 2, the silicon film 23 serving for prevention of leakage current in the semiconductor device.
Next, SiH.sub.4 and WF.sub.6 gases are introduced into the chamber, during time interval between t1 and t2 in FIG. 2, to form a first CVD tungsten film 20 having an excellent adhesiveness, followed by deposition of a second CVD tungsten film 21 having a larger thickness to fill the via-holes 16, using H.sub.2 and WF.sub.6 gases during time interval between t3 and t4. The H.sub.2 gas provides a higher deposition rate for the second tungsten film 21 compared to SiH.sub.4 gas. Thereafter, the first and second tungsten films 20 and 21 are etched-back to expose the Ti--Ni barrier films 19, followed by deposition of Al film 22 on the entire surface. The Al film 22 and Ti--Ni film 19 are then patterned to achieve Al interconnects 22 which are connected to diffused region 13 via tungsten films.
FIG. 3 shows another conventional blanket technique, wherein the tungsten film is deposited on an underlying interconnect layer to form tungsten plug within the via-holes. In this process, via-holes are formed on a first Al interconnect layer 25 overlying a silicon substrate 11. Then, an interlayer dielectric film 15A made of BPSG is formed on the entire surface, followed by patterning thereof to form via-holes exposing therethrough the underlying interconnects 25.
Next, Ti--Ni film 19, Si film 23, first tungsten film 20, second tungsten film 21 and overcoat layer are consecutively formed, as the first conventional case.
The conventional blanket processes for the tungsten film have disadvantages that particles are formed in the tungsten films, which causes a short-circuit failure in the semiconductor device, that a large contact resistance is formed between the tungsten film and the underlying interconnects to degrade the reliability of the semiconductor device, and that the throughput is relatively low.